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Поисковый запрос: (<.>K=MOSFET<.>)
Найдено 7 книг(а)/журнал(ов)
Показаны книги/журналы с 1 по 7


    Gili, Enrico.
    Asymmetric Gate-Induced Drain Leakage and Body Leakage in Vertical MOSFETs With Reduced Parasitic Capacitance [Электронный ресурс] [Text] / Enrico Gili, Kunz V. Dominik [et al.] // IEEE Transactions on Electron Devices [Электронный ресурс]. - USA
Кл.слова (ненормированные):
Аннотация: Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and
body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for
both the GIDL and body leakage from electrical measurements at temperatures ranging from .50 to 200 .C. The asymmetric body leakage is explained by a differe

Доп.точки доступа:
Kunz V. Dominik; Uchino Takashi; Al Hakim Mohammad M.; de Groot C. H.; Ashburn Peter; Hall Stephen

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    Raskin, Jean-Pierre.
    Analog/RF Performance of Multiple Gate SOI Devices: Wideband Simulations and Characterization [Электронный ресурс] [Text] / Jean-Pierre Raskin, Chung Tsung Ming [et al.] // IEEE Transactions on Electron Devices [Электронный ресурс]. - USA
Кл.слова (ненормированные):
MOSFET -- SOI -- аналогові, аналоговые
Аннотация: Multiple-gate devices, such as the planar double-gate (DG), triple-gate (TG), FinFET, Pi-Gate (PG), and Omega-Gate Silicon-on-Insulator (SOI) MOSFETs are potential candidates for achieving the performance targets of the International Roadmap of the Semiconductor Industry Association. In this paper, wideband experimental and three-dimensional simulation analyses have been carried out to compare the analog/RF performance of DG, TG/FinFET, PG, and single-gate (SG) SOI MOSFETs. The
characteristics of the multiple-gate devices were analyzed in the dc and ac regimes from subthreshold region to strong inversion and saturation regions. In both regimes, the advantages and limitations of the multiple-gate devices over the SG structure are discussed for channel length scaling well below 100 nm. To the authors’ knowledge, it is the first time that such extensive results and analyses are presented on the potential of these novel devices for highfrequency analog applications.

Доп.точки доступа:
Chung Tsung Ming; Kilchytska Valeria; Lederer Dimitri; Flandre Denis

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    Rittersma, Z. M. et al.
    Characterization of Mixed-Signal Properties of MOSFETs With High-k (SiON/HfSiON/TaN) Gate Stacks [Электронный ресурс] [Text] / Z. M. et al. Rittersma // IEEE Transactions on Electron Devices [Электронный ресурс]. - USA
Кл.слова (ненормированные):
CMOS -- CMOS-технологія, CMOS- технология, CMOS-technology, CMOS- Technologie -- MOSFET -- КМОН-технологія, КМОП-технология, CMOS-technology, CMOS-Technologie
Аннотация: The correlation between the stoichiometry of Hf-SiON gate dielectrics and mixed-signal properties of low-power MOSFETs is investigated. MOSFETs with gate length L down
to 100 nm were fabricated in a conventional fabrication flow with a thermal budget of 1000C.

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    Pagano, Rosario.
    Characterization, Parameter Identification, and Modeling of a New Monolithic Emitter-Switching Bipolar Transistor [Электронный ресурс] [Text] / Rosario Pagano // IEEE Transactions on Electron Devices [Электронный ресурс]. - USA
Кл.слова (ненормированные):
MOSFET -- біполярні транзистори ( БПТ ), биполярные транзисторы, bipolar transistors -- транзистори біполярні, транзисторы биполярные
Аннотация: This paper proposes the characterization, parameter estimation, and modeling of a monolithic cascode, which has been called emitter-switching bipolar transistor (ESBT), suitable for high-voltage applications. Such an innovative device is composed of a high-voltage power bipolar junction transistor (BJT) and low-voltage power MOSFET that are connected in cascode connection, with the MOSFET drain embedded inside the BJT
emitter. Being a four-terminal device, the ESBT requires a suitable characterization procedure aimed to identify the main electrical parameters relative to the inner BJT and MOSFET parts. Various test configurations that are needed to characterize the ESBT are
presented and discussed. The device has been characterized to derive a behavioral model implemented in the PSpice simulator in order to predict the device performances. The storage-time behavior has been investigated aiming to derive a suitable model devoted to the turn off switching of the ESBT. Such a model gives satisfactory r

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    Chan, C. -T.
    Characteristics and Physical Mechanisms of Positive Bias and Temperature Stress-Induced Drain Current Degradation in HfSiON nMOSFETs [Электронный ресурс] [Text] / C. -T. Chan, Tang C.-J. [et al.] // IEEE Transactions on Electron Devices [Электронный ресурс]. - USA
Кл.слова (ненормированные):
CMOS-технологія, CMOS- технология, CMOS-technology, CMOS- Technologie -- MOSFET -- КМОН-технологія, КМОП-технология, CMOS-technology, CMOS-Technologie
Аннотация: Drain current degradation in HfSiON gate dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The
degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the
second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a chargepumping technique. Finally, the effect of processing on high-k trap growth is evaluated.

Доп.точки доступа:
Tang C.-J.; Wang T.; Wang H. C.-H.; Tang D. D.

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    Vanhoucke, T.
    Analytical I–V Relationship Incorporating Field-Dependent Mobility for a Symmetrical DG MOSFET With an Undoped Body [Электронный ресурс] [Text] / T. Vanhoucke, Hurkx G. A. M. // IEEE Transactions on Electron Devices [Электронный ресурс]. - USA
Кл.слова (ненормированные):
МОН-транзистор, МОП- транзистор, MOS- transistor, MOS-Transistor -- польові транзистори, ПТ, полевые транзисторы, field transistors
Аннотация: A simple expression explicitly relating the surface potential to the surface electric field of a symmetrical double-gate (DG) MOS capacitor is proposed. The expression does not contain the floating-body potential as an implicit variable. It is used to derive, assuming the validity of the gradual-channel approximation, an analytical model expression for the current–voltage relationship of a DG MOS field-effect transistor. The effects of mobility
degradation at high vertical electric field and velocity saturation at high lateral electric field are incorporated. The model expression is continuously valid from the subthreshold to the quasi-linear regimes of operation and up to a well-defined drain saturation voltage. Beyond this saturation voltage, the gradual-channel approximation breaks down within a region near the drain end of the channel. The electric-field distribution within this region is estimated by solving a two-dimensional Poisson’s equation. Further implications of themodel are derived by si

Доп.точки доступа:
Hurkx G. A. M.

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    Bindu, B.
    Analytical Model of Drain Current of Si/SiGe Heterostructure p-Channel MOSFETs for Circuit Simulation [Электронный ресурс] [Text] / B. Bindu, DasGupta N., DasGupta A. // IEEE Transactions on Electron Devices [Электронный ресурс]. - USA
Кл.слова (ненормированные):
MOSFET -- аналітичні моделі, аналитические модели -- гетероструктури, гетероструктуры
Аннотация: An analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs is presented. A simple polynomial approximation is used to model the sheet carrier concentration (pHs ) in the two-dimensional hole gas at the Si/SiGe interface. The interdependence of pH s and the hole concentration at the Si/SiO2 interface (pS
s ) is taken into account in the model, which considers current flow at both the Si/SiGe and the Si/SiO2 interfaces. This model is applicable to compressively strained SiGe
buried-channel heterostructure PMOSFETs as well as tensilestrained surface-channel PMOSFETs. The model has been implemented in SABER, a circuit simulator. The results from the model show an excellent agreement with the experimental data.

Доп.точки доступа:
DasGupta N.; DasGupta A.

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